Method for testing digital memory devices

ABSTRACT

A method for testing a digital memory device, wherein the value ADR(1 . . . DN-1) XOR ADR(D . . . N) is entered into each memory cell of the memory device such that the sequence of numerical values entered depends on the address field (address bits D . . . N), and addressing errors in the higher-order address lines are detected.

The invention concerns a method for testing digital memory devices, inwhich

A certain number is assigned to each memory cell of the digital memorydevice, the quantity of selectable numerical values being defined by thenumber of memory cell locations, and the assignment of the numericalvalues occurring in such a way that a conclusion as to the address ofthe memory cells can be drawn from a numerical sequence from a pluralityof memory cells succeeding one another in the address field;

The respective numerical values assigned to the memory cells of thedigital memory device are written to them;

The memory cells are read and the read-out numerical value is comparedwith the respective assigned numerical value; and

If the read-out numerical value and the assigned numerical value are notidentical, an error message is generated.

A method of this kind is known from IMB TECHNICAL DISCLOSURE BULLETINVol. 32, No. 1, June 1989, New York, USA, page 220: "Method for addressfault detection." In this method, two numbers are used to check a memorywith four 1-bit wide memory cells; one of the numbers 0 or 1 is assignedto each memory cell, and from the sequence of assigned numbers of aplurality of memory cells succeeding one another in the address field, aconclusion can be drawn as to the address of the memory cell. Theassigned numbers are written into the respective memory cell, all fourmemory cells of the overall memory being written to in succession,beginning with the memory cell with the lowest address up to the memorycell with the highest address. The memory cells are then read out, andthe memory contents compared with the respective assigned number. Adifference between the read-out memory contents and the assigned numbermay be attributed to an addressing or memorization error. The assignednumbers are then stored again, this time beginning with the highestaddress. The memory cells are then read out again, and the memorycontents compared with the assigned number to check identity.

In another known method, the digital memory device test occurs in such away that the address of each memory cell is written into that cell, andthen the memory is read out again. Any errors which occur can bedetected by comparing the respective stored address with the read-outmemory contents, which must correspond to that address. Because of thehigh memory capacity of many circuits, this is a complex procedure.

In printed circuit boards, the most common embodiment of moderncircuits, short circuits occur particularly often between adjacentconductor paths. In the case of memories arranged on circuit boards,this often causes addressing errors to occur, i.e. the data are writteninto incorrect memory cells or multiple accesses occur to individualmemory cells under various addresses. Addressing errors of this kind arenot always detectable with the memory test just cited.

It is the object of the invention to indicate a method with which, indigital memory devices with memory cells comprising a plurality ofaddress bits, the aforesaid addressing errors can be recognized.According to the invention this is done, in a method of the aforesaidkind, by the fact that in a digital memory device with memory cells eachcomprising four address bits, the assignment of the numerical values tothe memory cells occurs as defined by

    Z=ADR(0,1, . . . S1) XOR ADR(S, . . . N),

where

Z=Numerical value in binary notation;

ADR=Address of the memory cell in binary notation;

N=Number of address bits in the memory cell minus one; and

S=2(location number of the memory location).

The invention will be explained in more detail with reference to twoFigures, which show by way of example:

in FIG. 1, an ordinary electronic circuit; and

in FIG. 2, the coding of test data.

The electronic circuit depicted in FIG. 1 comprises a memory 1 and amicroprocessor 2. The connection between the two functional groups isconstituted by a bus system consisting of an address bus A with fourdata lines and a data bus D with two data lines.

The two data lines correspond to the width of one two-bit memorylocation. The entire memory possesses 2⁴ =16 different memory cells. Itnot possible to unequivocally code these 16 different memory cells withonly the two data lines with a total of four displayable states.

In conventional test methods, therefore, only a portion of the addressinformation is written into the memory cells, for example the twolowest-order address bits. With this test method, however, addressingerrors that occur because of a short circuit of the top two addresslines are not detected, because for example memory cells 1, 5, 9, and 13contain the same information, and the effect of an addressing error ofthis kind is such that instead of memory cell 1, for example memory cell5 or 9 is written to.

According to the invention, the pure address information is not writteninto the memory cells, but rather the address information for the twolower-order address lines is linked to the address information for thetwo higher-order address lines. This occurs, for example, by means ofthe logical operation A1 XOR A2. The result of this operation isdepicted in FIG. 2. As is evident from FIG. 2, the sequence of numericalvalues for addresses 1-4 and 5-8 etc. is different. A conclusion cantherefore be drawn from this different sequence as to the location ofthe memory cell in the overall address space. This also makes itpossible, however, to detect errors of the kind described above. Forexample, when a short circuit of the topmost address line exists, duringthe memory test the information for cells 13-16 is written to thelocation of cells 5-8. The original information in these cells istherefore overwritten. When the memory is read out, what results istherefore the picture indicated in FIG. 2 in the "Error" column. Thesequence of read-out data is thus identical for memory cells 1-8 and9-16. This is an unequivocal indication that the fourth address line isdefective. Troubleshooting is therefore considerably facilitated.

What is claimed is:
 1. A method for testing a digital memory device, thedigital memory device including a first quantity of memory cells, eachof the memory cells having a distinct address, the method comprising thesteps of:defining a second quantity of predetermined values as afunction of the first quantity of memory cells; assigning thepredetermined values to each of the respective memory cells, thepredetermined values being assigned so as to determine the distinctaddress of each of the respective memory cells from a numerical sequenceof the distinct address of successive ones of the respective memorycells; writing the predetermined values to each of the respective memorycells; reading-out stored values from each of the respective memorycells; comparing each of the stored values read out with eachcorresponding one of the predetermined values; and generating an errormessage when one of the stored values read-out is different from thecorresponding one of the predetermined values, wherein each of thememory cells includes at least four address bits and the predeterminedvalues are assigned to the memory cells as follows:

    Z=ADR(0,1, . . . S1) XOR ADR(S, . . . N),

where:Z=an assigned numerical value, ADR=the address of one of thememory cells, N=the number of address bits in each of the memory cellsminus one, S=a location number of a memory location, the location numberhaving a value of 2.